Semiconductor processing and packaging techniques continue to evolve to meet industry demands for increased performance and reduced size. Electronic products, such as cell phones, smart phones, tablets, personal digital assistances, laptop computers, as well as other electronic devices, require packaged semiconductor assemblies having a high density of devices while having a relatively small footprint. For example, the space available for memory devices, processors, and other devices continues to decrease in electronic products providing a need to increase the density of semiconductor devices. The stacking of a semiconductor die is one technique used to increase the density. One potential challenge of stacking of semiconductor dies within a semiconductor package may be providing adequate electrical interconnects within the package and between the stacked semiconductor dies.
One technique for electrically connecting a semiconductor die to a supporting substrate, such as an interposer, or the like (herein collectively referred to as an interposer), is to use a bond wire. One end of the bond wire is attached to a bond pad of the semiconductor die (also referred to herein as a die) with the other end of the bond wire attached to a terminal pad of the interposer. Multiple bond wires may be used to electrically connect a single die with an interposer. As the size of semiconductor devices continues to decrease, the diameter of the individual bond wires may also decrease permitting the bond wires to be placed closer together, which may present disadvantages.
Bond wires are comprised of a conductive material, which may be an expensive material such as, but not limited to, gold, silver, platinum, nickel, copper, or alloys of these metals. The characteristics of the bond wire may be selected based on device specific processing or performance needs. A reduction in the diameter of the bond wires may provide a savings based on the material used in the bond wires, but bond wires having smaller diameters may present disadvantages as would be appreciated by one of ordinary skill in the art.
After stacked dies have been electrically connected to the interposer, the dies and bond wires may be encapsulated in another material, such as an epoxy mold compound, which protects the die and bond wires from environmental contaminants, while also fixing their locations relative to one another within a semiconductor device package. Various encapsulants may be used to encapsulate and protect the dies and bond wires. For example, a polymer material, such as an epoxy, may flow over and around the bond wires and semiconductor die and may be cured after covering the bond wires and dies. However, the flowing epoxy material may displace, or even deform, the bond wires, which has been termed as “sweep.” As bond wires are continually placed closer together, sweep of the bond wires caused by the flowing encapsulating material may cause bond wires to contact one another creating a short. Bond wires having smaller diameters may be more susceptible to sweep, which may cause the bond wire to break or cause a bond wire to contact an active surface of the semiconductor die creating a short. Thus, sweep of the bond wires may cause the semiconductor device to malfunction or fail.
FIG. 1 is a schematic of a semiconductor device 100 comprised of two dies 120, 130 stacked on top of an interposer 110. The bottom side of the interposer 110 includes solder balls 101 that may be used to electrically connect the semiconductor device 100 to an external device. An adhesive layer 105 may be used to bond the lower die 120 to the interposer 110. Bond wires 121 electrically connect the first die 120 to the interposer 110 and bond wires 131 electrically connect the second die 130 to the interposer 110. Each bond wire includes a “loop height,” “W,” which is the distance required to bend the bond wire 180 degrees so that the bond wire can extend off the die 120, 130 and then extend down to the interposer 110. An encapsulating material may be provided over the semiconductor device 100, but the semiconductor device 100 of FIG. 1 is shown without an encapsulating material for illustrative purposes.
The semiconductor device 100 has an overall height “Z”, which may be comprised of the height of the solder balls 101, interposer 110, adhesive 105, first die 120, and second die 130. In addition, the loop height, W, of the bond wires 131 also adds to the overall height Z of the semiconductor device 100. The loop height of a bond wire may vary depending on the diameter of the bond wire as well as the material of the bond wire as would be appreciated by one of ordinary skill in the art. Encapsulant material 140, such as epoxy, may be used to encapsulate the components on the device. As shown in FIG. 1, the encapsulant 140 must extend at distance above the loop height W of the bond wires 131 to ensure that the wires do not protrude out from the material 140. The height of the material 140 above the loop height, W, also adds to the height Z of the device 100 as shown in FIG. 1. As discussed above, it may be beneficial to provide a semiconductor device 100 having a high density of devices, which reduces the overall footprint of the device, while having a reduced height Z. The semiconductor device 100 may not have a sufficiently reduced height, Z, and overall footprint for some applications.
FIG. 2 is a schematic of a semiconductor memory device 200 comprised of four memory dies 220, 230, 240, 250 stacked on top of an interposer 202. The memory dies 220, 230, 240, 250 may be comprised of non-volatile memory dies. For example, the memory dies 220, 230, 240, 250 may specifically be NAND-type flash memory dies. A controller 210 is positioned between the memory dies 220, 230, 240, 250 and the interposer 202. Any suitable controller 210 may be used. For example, the controller 210 may be an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), an application specific instruction-set processor (ASIP), complex programmable logic device (CPLD), or other logic chip as would be appreciated by one of ordinary skill in the art having the benefit of this disclosure that may interface the memory dies 220, 230, 240, 250 with an external host device. The controller 210 may also perform various other operations, such as, but not limited to, provide error correction, manage data storage, mapping, and/or garbage collection. An adhesive layer 205 is used to bond the controller 210 to the interposer 202 and the controller 210 may be electrically connected to the interposer via a bond wire 211. The adhesive layer 205 may need to be at least 100 microns in order to adequately bond the controller 210 to the interposer 202. The semiconductor device 200 has an overall height Z, which is comprised of the height of the solder balls 201, interposer 202, adhesive 205, controller 201, first die 220, second die 230, third die 240, and fourth die 250. The overall height Z of the device 200 would also include any encapsulant, which has not been shown in FIG. 2 for clarity. In addition, a loop height (not labeled on FIG. 2) of bond wire 251 may also add to the overall height Z of the semiconductor device 200. As discussed above, it may be beneficial to provide a semiconductor device 200 having a high density of devices, which reduces the overall footprint of the device, while having a reduced height Z. The semiconductor memory device 200 may not have a sufficiently reduced height, Z, and overall footprint for some applications.
Additional drawbacks and disadvantages may exist.
While the disclosure is susceptible to various modifications and alternative forms, specific embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the disclosure is not intended to be limited to the particular forms disclosed. Rather, the intention is to cover all modifications, equivalents and alternatives falling within the scope of the invention as defined by the appended claims.